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The Open Graphic Project is dedicated to producing open source Graphics Cards with Open source Drivers. Please document information regarding our development tools here to assist new contributers.

Subversion

Subversion is a centralized versioning system. It lets many developers work on the same tree of source files, keeps track of changes, and provides means of solving conflicts between concurrent edits.

Quick Start with OGP Read - Only Access

First, if you don't have the svn command on your machine, you will need to install subversion. This is available from http://subversion.tigris.org/. It is commonly available in the package repositories (at least on Linux distributions).

OGP has a public repository. To check it out, go to the directory where you want to store the top level directory. Then type

The last argument is the local directory, so now you should have a directory called ogp. If you leave out the last argument, the last component of the URL (trunk) will be used.

Once you have done this, you can at any time go into the directory and type

to update to the latest version. If you change some file and want to contribute the changes back to the project, you can obtain a patch with

If you drop the file name, then you get a patch for all files you have changed in the current directory, and recursively all subdirectories.

To access an older version of a single file, eg, r94 instead of r95

If you want to get revision 94 inside a working copy,

Checking out outside a working copy only works for directories, but you can write

and direct the output to an appropriate file.

You will find a comprehensive guide to Subversion at http://svnbook.red-bean.com/.

HDL Editors

While you can easily write verilog or VHDL using an text editor, an editor that knows RTL languages can save you from simple errors.

http://www.nedit.org/
Under Preferences, you will find 'Language Mode' where you can select Verilog.

http://www.kate-editor.org/
A KDE editor with a Verilog syntax highlighting option under Tools -> Highlighting -> Hardware.

HDL Simulation and Synthesis Software

FOSS

GTKWave Waveform Viewer

• GTKWave 3 http://home.nc.rr.com/gtkwave/
• Windows http://www.dspia.com/gtkwave.html and http://www.geocities.com/SiliconValley/Campus/3216/GTKWave/gtkwave-win32.html

GTKWave is available with many distributions. In Mandrake 10.1, it installs under the menu entry More Applications, Sciences, Other.

Use GTKWave to view VCD files produced by Verilog Simulators. When viewing any waveforms you need the signal names. With some older versions it has a nice "Add signals" button on the tool bar. (Sept 06) For newer versions You have to select Search|Signal Search Tree in the menu to get a dialog that will let you display the signals if you twist its arm a bit. Click on the [+] markers to expand the tree as necessary, click on the signal you need, click Append. Repeat as necessary.

gpl-cver Verilog Simulator

• http://www.pragmatic-c.com/gpl-cver/
• (portage: gplcver)

P. Urkedal 28-8-06: (This) accepts the Samsung memory simulator model.

Icarus Verilog

The command line tool Icarus Verilog can simulate and does generic synthesis with .edif and .xnf output. Available for Linux, Windows and Mac.

• Icarus Verilog Home page
• Icarus Verilog 8.0 Binaries

Robert (Dec06): Support is available in the gEDA mailing list and Stephen Williams steve AT icarus DOTCOM is the main author.

If you use Debian, Ubuntu, or Gentoo, you can easily get Icarus Verilog from your package management system, rather than installing it manually. This is likely true for other distributions as well.


using icarus to 'compile' and 'execute' a design:
Mailing list May 06. T. Miller: a random piece of code will look like this:

initial begin
clock_1x = 1;
forever begin
#10;
clock_1x = !clock_1x;
end
end
iverilog spi.v spi_test.v
./a.out

And here's how to view the wave forms:

Troubleshooting

A programmer queried: I got the following output when executing a.out:

0 write=1 read=0 addr=0003 in=ff00 out=xxxx
1 write=0 read=1 addr=0003 in=ff00 out=xx00

I assume those 'x' means 'Don't Care', but why am I getting those?
It's even strange because it sets 0 accordingly.

R. Osial (jun 06) X can mean two different things: Unitialized value and conflicting signals. (Don't care is in the verilog syntax, somewhat. See casez and casex for more information).

In this simulation, the first xxxx at time 0 resulted from uninitialized memory. The xx00 at time 1 came from two conflicting assignments to the same net. (out=0000 and out=1100). The simulator was able to resolve the two low bits to 00. However, the two high bits are assigned 0 and 1 at the same which the sim can't resolve to a 0 or 1. So instead, it assigns the bits an X.


gtkwave test.vcd

There's code you have to put into the test module to make it output waves:

initial begin
$dumpfile( "test.vcd" );
$dumpvars;

#5000; // duration of simulation
$finish;
end
End quote.

Proprietary

Lattice Semiconductor

• ispLEVER from Lattice. The free "Starter" edition is Windows-only, but you may manage to use it under Wine.
  • How to install and use ispLEVER Starter under Wine
  • In the Subversion repository (see above) you will find a batch wrapper 'ispsynpc' for the Synplify synthesizer, which transforms error messages into a format which Vim and Emacs understand. Type 'perldoc ispsynpc' for instructions.

Xilinx

• 6.3 is apparently the first for Linux and Windows and is called one of the 'classics' which are for free. Regretably the Xilinx Download only included the Windows version (requires reg) http://www.xilinx.com/ise/logic_design_prod/classics.htm James Richard Tyler noted: If you are logged in, you can get them here:
  • http://direct.xilinx.com/direct/webpack/63/WebPACK_63_fcfull_i.exe
  • http://direct.xilinx.com/direct/swhelp/series6/63i_sp3/6_3_03i_pc.exe
  • Benjamin found the application note XAPP473 - Using the ISE Design Tools for Spartan-3 FPGAs - http://direct.xilinx.com/bvdocs/appnotes/xapp473.pdf
  • The free version for download is Windows-only, but you may manage to use it under Wine. Xilinx 6.3i Webpack under Wine
  • Michel Brabants pointed to this as a page about running the Xilinx webpack 6.3 using Wine and the Debian-distribution.
  • http://gentoo-wiki.com/HOWTO_Xilinx

Hardware Tools and Tips

Programming Xilinx

in the Newsgroups: comp.arch.fpga with the subject: Xilinx Platform cable USB and impact on linux without windrvr, a developer reported:
quote:
After being bitten by windrvr once again (it did not compile after a kernel upgrade), I decided to see if I could get the Xilinx USB cable and impact working without a kernel module. To achieve this, I have written a wrapper library for impact which maps calls to windrvr to the userspace libusb-library which should be available on all modern linux distributions. With this wrapper I am able to program a XC3S1500 in 2 seconds, which is the same time it takes when using windrvr. The library has been developed and solely tested against impact from ISE Webpack 9.1i SP1 and will very likely not work with older versions (pre 9.1i).

The library source can be downloaded at: http://cvs.zerfleddert.de/cgi-bin/viewcvs.cgi/usb-driver.tar.gz?view=tar
or browsed at: http://cvs.zerfleddert.de/cgi-bin/viewcvs.cgi/usb-driver/

I have also put a precompiled version (built on Debian Etch) at: http://www.rmdir.de/~michael/xilinx/

Please report back if this library is useful and works for you. Maybe this helps XILINX to decide that they do not need to use windrvr
for easy USB access, as most parts of my library are only there to provide a compatible replacement for windrvr functions and are not
needed when directly accessing libusb from within an application program.
endquote.

JTAG

At this stage we have not tested these and cannot recommend a particular JTAG tool. However this is a collection of comments from the list:

D. Jones: the Slug community:
http://www.nslu2-linux.org/
By necessity, some people there have had far more experience with JTAG than they ever wanted.

Daniel: I've found one supplier / developer company in Czech republic, which makes an universal usb programmer (pic,jtag,avr-isp)..
http://asix.cz/a6_presto.htm
(the page is in czech)

Price is 2000 CZK = $92 The specs says jtag support, but the drivers are win-only. The speed is approx 64kByte in 3s.

We might ask them if it supports multiple devices on the chain and if they would release the protocol so we could write Linux drivers?

Dag suggested: http://www.google.com/search?complete=1&hl=en&q=cheap+jtag+usb+cable&btnG=Google+Search

Peter: It should be possible to build a parallel port <-> JTAG converter using a PIC or an 8051 and not much else. Should be a lot faster than the "wiggler"/bit banger type. The limit would then be how fast the microcontroller could accept a byte and output it serially and not how fast the data could be transferred out of the printer port and across the printer cable.
(Ok, a strict traditional 8051 won't be all that fast: a 12 MHz clock translates to 1µs for the fastest instructions. Special code for each byte value means that the fastest code sequence can be used for each. As far as I can see that's two or three 1µs instructions per bit, depending on whether the data transitions or not. There's a maximum of four data transitions per byte so that's 4+16=20 instructions of 1µs each. So 20µs per byte is 50kB/s, ignoring all overhead. Not particularly fast after all. Happily, there are plenty of modern 8051s that can either use a faster clock or use fewer clock periods per cycle!)

Robert: I got the JTAGkey-Tiny (http://www.amontec.com/jtagkey-tiny.shtml) for 29 euro a couple of months ago for a reversing project, but in the end I never used it. It has a Linux driver, there's also a more expense (99 euro) version with a wider voltage range.

Simon mentioned: their Linux drivers appear to consist of a tgz file with a single binary file in it.

Attila (Feb 07): The best looking options are the JTAGkey*1 and JTAGkey-tiny*2 from amontec and the USBJTAG*3 board from Hubert Hölg. All three together with the Open-OCD*4 software package.

All three systems use a FT2232 USB to Serial adapter chip in bit-bang mode.

Unfortunately, i didn't had much time to look up what Open-OCD exactly does and how it could be used. As soon as i have some time, i'll check it out, order either one of the JTAG-key's (probably the -tiny) or build myself a USBJTAG board (though this would cost more than the JTAGKey-Tiny). Whether these boards can be used to program a Xilinx or Lattice FPGA is still an open question, but it should be only a matter of software than anything else.

1 http://www.amontec.com/jtagkey.shtml
2 http://www.amontec.com/jtagkey-tiny.shtml
3 http://www.fh-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html
4 http://openocd.berlios.de/web/