OGD1 components guide

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Componments and connexions

A) 2x DVI transmitters (pair A)

B) 2x DVI transmitters (pair B)

C) 1x 330MHz triple-10 bit DAC (behind)

D) 1x TV chip

Conexant CX25874
Video Encoder

http://www.conexant.com/servlets/DownloadServlet/DSH-200670-001.pdf?docid=671&revid=1

E) 2x4 256 megabit DDR SDRAM chips (front, behind)

DDR RAM
http://www.samsung.com/products/semiconductor/DDR_DDR2/DDRSDRAM/Component/256Mbit/K4H561638F/K4H561638F.htm

Datasheet:
http://www.samsung.com/Products/Semiconductor/DDR_DDR2/DDRSDRAM/Component/256Mbit/K4H561638F/ds_k4h56xx38f_tsop2_rev14.pdf]

T. Miller Jun 06 a simulation model for the chip we're using,here:
http://www.samsung.com/Products/Semiconductor/DDR_DDR2/DDRSDRAM/Component/256Mbit/K4H561638F/k4h561638f_0501.tar
To configure the model for the particular chip we're using, I added this to the top of the k4h561638f_a2_0501.v file:

`define M256
`define X16
`define SCC
There are some errors showing with icarius apparently from lack of event control support.


Memory Pin Out List

T. Miller (Jun 06) We are driving pairs of 16-bit DDR chips together as a unit, so it's basically like driving a single 32-bit chip.
For each group of 8 data lines (DQ), there is:
A single data strobe (DQS) that is just a data clock and;
A single data mask (DM) that is a byte-enable for writes.

Each pair of chips has a single set of control lines (address, ras,
cas, we(wr), bank, pclock, and nclock).

(...) If anyone wants to help (with a pin out list), just post changes to the list. You can have openoffice split pieces of spreadsheet out in CSV format, which I can then paste into place, and if there are corrections, just explain them.

the signals must be grouped properly according to the memory chips on pages 7 and 8 of the schematic. Note the resistors on page 9 for the name changes from M to MEM for some pins.

F) 1x Main FPGA

Verilog and EDIF netlists for the OGD1 board can be found here:
http://www.traversaltech.com/ogd1_images/ogd1_netlist.zip

Xilinx Sparten XC3s4000

Howard, Andy, and Timothy tested whether we would be able to fit an OGA-compliant design into a Lattice ECP2-50. Our determination is that the Xilinx 3S4000 is the only chip available within the next 6 months that will meet our needs.

Some results of this change:
- 10-bit triple-DAC fully connected
- Some extra user I/O signals
- Potentially wider local bus between the two FPGAs
- More versatility on the signal types for the user I/Os
- Increase in OGD1 parts cost
- Potential to populate 3S5000, if necessary
- ISE 6.3i to synthesize for the 3S4000. Source OGPN10

Datasheet

• http://www.xilinx.com/bvdocs/publications/ds099.pdf

G) 1x XP10 FPGA

XP10
The Lattice XP10 Non-volatile, reprogrammable FPGA is used for PCI communication.

http://www.latticesemi.com/dynamic/view_document.cfm?document_id=9418

H) 1x SPI PROM 8Mbit

J) 1x SPI PROM 16Mbit

K) 3x 500MHz DACs (optional)

L) 1x 64-bit PCI-X edge connector

M) 2x DVI-I connectors

N) 1x S-video connector

O) 1x 100-pin IDC expansion bus connector

IDC Connector
T. Miller Jul 06: The connector is for user I/O. If someone else wanted to design a board that connected to that (directly or indirectly), that would be okay. Also, it's primarily not cost-effective for us to provide things on daughter boards for OGC. For OGD1, it depends on the needs. OGD1 has holes for a reinforcement bar that you can use to stiffen it, along with an extender board, if you need to.

P)Other Components

soTiny single bit bus switch
http://www.pericom.com/pdf/datasheets/PI5C3302.pdf